Every answer has to travel.
This is an H100-class AI accelerator: one 814 mm² slab of silicon with 80 billion transistors, ringed by towers of stacked memory. Chips like this answer your chatbot questions. To see why a different kind of chip matters, we first need to see how this one thinks.
Mostly, it multiplies.
An AI model is a giant table of numbers called weights. Answering means multiplying your input by those tables, over and over: multiply, add, repeat.
A model with 70 billion weights does about 140 billion multiply-adds for every word it writes. Everything else on this page is about how fast, and at what energy cost, a chip can do that.
Math made of switches.
A digital chip stores every number as a row of bits: ones and zeros, each held by transistors that are either on or off. A multiply is a little machine of thousands of transistors flipping in a precise order, once every clock tick.
An H100 packs 528 tensor cores, little grids of multiply-add units built to chew through blocks of numbers at once.
132 neighbourhoods, one river.
Zoom into the die and it looks like a city. There are 132 identical blocks called streaming multiprocessors (SMs), each with four tensor cores and its own small, fast memory. Through the middle runs a 50 MB river of shared cache.
The city is fast. But it has a problem: the numbers it needs mostly don't live here.
The numbers live in the towers.
The weights don't fit on the die. They sit in HBM, high-bandwidth memory built as stacks of DRAM chips. A wafer-thin silicon interposer carries thousands of wires between the towers and the city.
Follow one number.
Before a weight can be multiplied, it has to make a trip: out of a DRAM cell, down the stack, across the interposer, through the caches, into the registers, and finally into a tensor core. Each checkpoint costs energy. Watch the meter.
Energy per 32-bit access at 45 nm (Horowitz, ISSCC 2014). Modern chips are cheaper per step, but the ratio between moving and computing has stayed stubborn.
The cores sit and wait.
To keep every tensor core busy, an H100 needs about 295 operations of work for every byte it pulls from memory (989 trillion ops ÷ 3.35 trillion bytes per second).
A chatbot writing one word at a time does roughly one operation per byte of weights. So for a single conversation, the math units are idle more than 99% of the time, stuck in traffic. Data centres batch hundreds of users together to hide it.
This is the von Neumann bottleneck: memory here, compute there, and a bridge in between.
Most of the watts move data.
Power climbs up through hundreds of pillars into the die. Most of it isn't spent on the math. It goes to charging and discharging wires to move ones and zeros around, and all of it leaves as heat.
One H100 at 700 W, running all year, uses about 6.1 MWh, and data centres run them by the tens of thousands.
What if the memory
did the math?
No towers. No bridge.
In October 2025, a team at Peking University led by Sun Zhong published an analog chip in Nature Electronics. Inside, there's no separate memory and no separate math unit. There's a grid of wires with a tiny memory cell at every crossing, and the grid itself does the computing.
One cell, one number.
Each crossing holds a resistive memory cell (RRAM): a sandwich of metal, a thin oxide layer, and metal. A voltage pulse grows a tiny conductive filament through the oxide. A thicker filament lets more current through.
That ease of flow, its conductance, is the stored number. It stays put with the power off, and it can be read without moving it anywhere.
Every multiply at once.
Step 1. Converters (DACs) turn your input numbers into voltages on the rows.
Step 2. At every cell, Ohm's law does a multiply for free: current = conductance × voltage.
Step 3. On every column, Kirchhoff's law adds the currents together.
Step 4. Converters (ADCs) read the column currents back out as numbers.
A whole grid of multiply-adds happens in one physical instant. The weights never move.
Close the loop. Let it settle.
Feed the outputs back to the inputs through amplifiers and the circuit stops being a calculator. It becomes an equation solver: it physically settles on the answer to Ax = b, the kind of problem behind 6G signal detection, simulations and AI training.
Analog answers are fuzzy, so the chip refines them. A second array, with numbers split into bit slices, checks the error and corrects it until the result matches digital precision (reported at 24-bit).
Two ways to think.
Reported by the team against top digital processors, H100 included, on matrix-equation workloads at the same precision.
What it isn't, yet: a GPU replacement. It's a lab system (an 8×8 inversion array, 16×16 problems solved), built for matrix equations, not for running a whole chatbot. *The 40 nm figure comes from secondary reporting.
From 40 nm to 2 nm.
The H100 is built at 4 nm-class. This analog chip worked at 40 nm-class, a process from around 2008. So what happens if it moves to modern nodes? Pick one:
What shrinks well: the converters and control logic. They're ordinary transistors, and studies find they can burn 80–96% of an analog chip's energy. What fights back: thinner wires have more resistance and distort the currents, the filament physics doesn't shrink like a transistor, and cell-to-cell variation grows. RRAM itself ships at 22 nm today, not at 2 nm.
energy gain = 1 / ((1 − f) + f / s) · f ≈ 0.9 of energy in converters · s = converter gain at that node
density gain = 1 / (0.3 / cell + 0.7 / logic) · 70% of area in periphery · cell capped at 22 nm-class
This is a scenario, not a measurement: our estimate from logic-density and published RRAM data. GPUs shrink too, so the head-to-head gap doesn't simply multiply.
Stop moving the numbers.
The likely future isn't a 2 nm RRAM chip. It's a stack: analog memory layers built above (or bonded onto) advanced-node logic, so the converters get the newest transistors and the numbers never leave home. Whether it wins depends on wires, variability and software. The physics is already on its side.